llama.cpp b9965: Hexagon ARGSORT gets bitonic sort in HVX registers

llama.cpp b9965 ships a Hexagon DSP ARGSORT rewrite — bitonic sort in HVX registers handling up to 1024 elements per pass, with specialized fast paths for common tensor sizes.

What changed:

• Hexagon ARGSORT (PR #25512): generic sorting replaced with bitonic sort in HVX registers, up to 1024 elements, plus specialized functions for common tensor shapes
• hex-sort fixes: inverted vror operations corrected, tracing and local context added
• Build matrix expands: Windows x64 gets CUDA 13.3 DLLs alongside existing CUDA 12.4, ROCm 7.2 on Ubuntu, SYCL FP16, Windows arm64 OpenCL Adreno, Ubuntu s390x CPU

ARGSORT runs in attention masking and sampling paths. On Hexagon targets — Qualcomm Snapdragon DSPs — faster small-tensor sorting compounds through every token decode. Bitonic sort maps cleanly to HVX vector registers, which is why the specialization matters: common tensor sizes skip generic dispatch entirely.

Prebuilt binaries for 20+ platform/GPU combinations are on the b9965 release page — including CUDA 13.3, Vulkan, SYCL FP16, and OpenCL Adreno for Windows arm64.